Advanced microelectronic interconnects can include multiple stacked layers of dielectric films. Due to the large number of interfaces between dielectric layers, interfacial adhesion is critical to ensure a reliable and robust structure that can survive the various fabrication processes and conditions used to fabricate the desired device. With the advent of mechanically fragile low k and ultra low k dielectric currently being used or explored in these advanced applications, the issues of maintaining adequate interfacial adhesion as well as overall fracture toughness of the multilayer stack is becoming more important.
FIG. 1 provides a prior art device structure generally designated by reference numeral 10 that includes multiple stacked dielectric layers. The device structure is exemplary and is provided to illustrate an interface between the dielectric layers, which are of the type commonly formed during the fabrication of advanced microelectronic devices. The structure 10 generally includes a substrate 12, a first dielectric film 14 disposed on the substrate, and at least one additional dielectric layer 16 disposed on the first dielectric layer. As shown, an interface 18 formed between the first and second dielectric film is substantially smooth, which can result in mechanical failure during fabrication of the device in which additional layers are added and patterns are formed thereon. For example, adhesion failure and fracturing of one or more the layers can occur.
Tailoring of the interfaces by appropriate chemical and/or plasma treatment to provide improved wetting of the layers is known in the art. For example, U.S. Pat. No. 6,214,479 to Mori et al., U.S. Pat. No. 7,025,826 to Selvamanickam et al., and US Pub. Appln. No. 2005/0167261A1 to Deusthmann et al. describe methods employing an inert or reactive gas ion exposure and bombardment of a substantially smooth interface surface to provide physical surface topography such that an additional layer disposed thereon will have a complementary topography, thereby providing improved adhesion and fracture toughness. However, the topography provided by these treatments is generally random. Moreover, the morphology in the lateral and vertical directions is difficult to control and reproduce. Still further, these processes are generally substrate dependent.
The various known surface treatments such as those noted above can also lead to undesirable chemical modification of the substrate depending on the plasma gases employed. For example, it is generally difficult with these processes to localize the chemical modification caused by plasma exposure of the substrate to the top surface (the interface) only. In the case of low k dielectric films of interest for chip applications, the interconnect electrical characteristics (e.g., dielectric constant (k) and breakdown fields) can be significantly and undesirably degraded as a result of the plasma exposures. A good example of this has been observed with the use of mild oxidizing plasma treatments to provide improved adhesion on porous organosilicate dielectric films. Although the plasma treatment renders the organosilicate surface more hydrophilic and wettable, significant damage occurs throughout the depth of the organosilicate low k dilectric making this type of process unsuitable. Damage manifests itself in the form of a higher dielectric constant (higher k) and lowers the breakdown strength of the dielectric. Thus, the use of the above noted chemical means to enhance adhesion and fracture toughness in these structures is limited in practicality.
Rough textures have also been achieved in polymer sheets using mechanical profiling tools such as knurled rollers. However, the use of mechanical profiling tools is generally impractical for use with interconnecting structures with thin dielectric layers because of the fragility of the microelectronic components and substrates, many or which are processed on fragile silicon wafers and comprise thin dielectric and metal films.
It is also known that mechanical interlocking between layers can be used to enhance adhesion in macroscopic structures such as fiber and laminar composite systems. However, in comparison with a carbon fiber in a fiber/epoxy composite which may be a few to ten microns in diameter, a typical layer of ultra low k dielectric interconnect stack may be only 100 to 200 nanometers (nm) in thickness. Thus, the scale of surface corrugation one has to achieve in these films has to be on the order of several nanometers in depth. Further, since the metal feature sizes embedded in these structures are on the order of 50 to 100 nm in lateral extent, the wavelength of these corrugations in plane has to be on this order as well. A high corrugation density (i.e., short wavelength) is also desirable to maximize the total contacted interface area for a given projected interface area between the layers.
Thus, it is clear that suitable methods to achieve well controlled, non-damaging, reproducible, nanoscale corrugations in substrates and thin film coatings of interest in microelectronics is desirable and is not readily achieved by methods known in the current state of art. Such a surface topography will greatly enhance the effective contact surface area between a substrate or an underlying film and an overlying film. The force needed to separate the overlayer film to the underlayer film will correspondingly be increased in proportion to the contact surface area for a given interfacial adhesion strength per unit area. Further, an additional benefit will be realized due to the fact that any propagating interface crack will be blocked and perhaps deflected by the nanoscale corrugations leading to a tortuous crack front that normally leads to increased fracture toughness.
Accordingly, there remains a need in the art for methods that provide surface topography to interface regions of interconnect stacks in a controlled and reproducible manner so as to provide increased adhesion and fracture toughness. Desirably, the methods should provide minimal impact on properties of the other components.